Microsemi Corporation Backend Implementation Engineer in Bangalore, India

About the Job:

Division: Advanced Enginerring Services

Location: Bangalore, India

Job Responsibilities:

  • Execute implementation plans to synthesize, implement Design For Test, and close timing on complex digital integrated circuits at the block, subsystem or chip level, which are coded in VHDL/Verilog/SystemVerilog.
  • Use metric-driven techniques to help ensure first-pass working silicon.
  • Design, implement and maintain synthesis, DFT and Static Timing scripts using best-in-class methodologies.
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
  • Communicate regularly with the project teams world-wide to resolve issues, communicate status and solve technical problems.

Job Qualifications:

This position requires at least B.E/B.Tech in Electronics with 0-4 years of ASIC development experience in a fast paced environment with following experience.

  • Excellent analytical skills and knowledge of deep-submicron chip aspects
  • Experience with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization, closing timing on either block level or chip level is an added plus.
  • Good scripting skills; knowledge of synthesis & timing algorithms.
  • Backgrounds on standard cell, layout, timing/power views, and characterization would be added advantage.
  • Must be able to work autonomously.
  • Excellent oral and written communications skills.

Job Qualifications:

This position requires at least B.E/B.Tech in Electronics with 0-4 years of ASIC development experience in a fast paced environment with following experience.

  • Excellent analytical skills and knowledge of deep-submicron chip aspects
  • Experience with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization, closing timing on either block level or chip level is an added plus.
  • Good scripting skills; knowledge of synthesis & timing algorithms.
  • Backgrounds on standard cell, layout, timing/power views, and characterization would be added advantage.
  • Must be able to work autonomously.
  • Excellent oral and written communications skills.

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled