Microsemi Corporation Senior Mixed Signal Layout Engineer in Bangalore, India

About the Job:

Division: Mixed-Signal Development Group, Advanced Engineering Services

Location: Bangalore, India

Title: Senior, Mixed Signal Layout

The Mixed Signal Development Group is responsible for delivering analog and mixed-signal IP to divisions within Microsemi. We work with leading edge CMOS processes to produce analog integrated circuits for wireline and RF applications. From T1/E1 to 56Gb/s SERDES, we enable technology that allows Microsemi's products to interface to the outside world.

As a member of the Mixed Signal Layout team, you will work in collaboration with a Mixed-Signal Design Engineer on circuits such as high speed (GHz) receivers, transmitters, PLLs, analog to digital converters, digital to analog converters, and other analog building blocks. You must consider the impact of microfabrication processes, electro migration, electrostatic discharge and other physical effects of leading edge CMOS processes used in mixed-signal (65nm, 40nm, 28nm, 16nm etc.). You will also consider the interaction of your block with the other blocks around it. You will run verification sets (DRC, LVS, physical effects) and provide support to other members of the team.

Responsibilities:

  • Layout of CMOS analog and mixed-signal integrated circuits in collaboration with the circuit designer and under the supervision of a lead/manager.
  • Creation and verification of the layout with state-of-the-art CAD tools.
  • Conduct reviews and document deliverables.
  • Mentor junior engineers.

Qualifications:

  • Bachelor's Degree or Masters in Electronic is strongly preferred.
  • 5+ years of industry experience in analog and mixed-signal layout design.
  • Experience in layout of high-speed (GHz) mixed-signal circuits: receivers, transmitters, ADC, DAC, PLL, etc. is an asset
  • Understanding of the design of mixed-signal CMOS amplifiers, current mirrors and bias circuits
  • Knowledge of CMOS semiconductor physics and microfabrication processes and impact of layout on the performance of circuitry in leading edge CMOS processes
  • Experience with electro-migration (EM) and electrostatic discharge (ESD) in high-speed mixed-signal blocks is a must.
  • Experience with Cadence Design Environment, Mentor Verification tools and similar vendor tool packages is an asset
  • Experience with reading and writing technical documentation such as engineering specifications, schematics, procedures, and work instructions.
  • Strong written and oral communication skills
  • Ability to work in a team environment and mentor junior engineers.

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled