Microsemi Corporation Design Implementations Engineer in Burnaby, British Columbia

Microsemi is currently looking for an Implementation Engineer to join our Implementation team in our Burnaby BC office. As a key member of Microsemi's Implementation team, the successful candidate will execute Microsemi's Chip development methodologies which include block level place and route, physical design verification, macro level test structures, digital wrapper development for analog cells, synthesis, static timing, and ATPG flows for high-performance devices. The successful candidate will also work closely with our customers to support them through Microsemi's Chip development flow, and work with other Microsemi groups across disciplines (CAD, Packaging, Mixed Signal, Operations, and Design) to ensure the Chip is successfully completed. Our team uses state-of-the-art tools and flows to build large and complex SOCs/ASICs.

Responsibilities: * Develop and execute plans to synthesize, implement Design For Test, run physical design and/or close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 100M+ gates), which are coded in VHDL/Verilog/System Verilog. * Use metric-driven techniques to help ensure first-pass working silicon. * Analyze log and report files to ensure tools are achieving the required results and make adjustments to the scripts to get the required results within the scheduled milestones. * Communicate regularly with the project teams world-wide to resolve issues, communicate status and solve technical problems.

This position requires at least 4-year degree in Electrical or Computer Engineering with 0-2 years of ASIC development experience in a fast paced environment.

  • Excellent analytical and debugging skills and the ability to proactively solve issues.
  • Proven ability to thrive on, learn and adapt to new methodologies and technologies
  • Good software and scripting skills; knowledge of synthesis & timing algorithms
  • Backgrounds on standard cell, layout, timing/power views, and characterization desired.
  • Must be able to work autonomously, but ensure to inform management of current status.
  • Be able to understand Verilog and VHDL languages
  • Excellent oral and written communications skills.
  • Background in 28nm process or lower a plus
  • Python/PERL/TCL language knowledge a plus

Equal Opportunity Employer Minorities/Women/Protected Veterans/Disabled